-
What is pipelining?
-
What are the five stages in a DLX
pipeline?
-
For a pipeline with ‘n’ stages,
what’s the ideal throughput? What
prevents us from achieving this
ideal throughput?
-
What are the different hazards? How
do you avoid them?
-
Instead of just 5-8 pipe stages why
not have, say, a pipeline with 50
pipe stages?
-
What are Branch Prediction and
Branch Target Buffers?
-
How do you handle precise exceptions
or interrupts?
-
What is a cache?
-
What’s the difference between
Write-Through and Write-Back Caches?
Explain advantages and disadvantages
of each.
-
Cache Size is 64KB, Block size is
32B and the cache is Two-Way Set
Associative. For a 32-bit physical
address, give the division between
Block Offset, Index and Tag.
-
What is Virtual Memory?
-
What is Cache Coherency?
-
What is MESI?
-
What is a Snooping cache?
-
What are the components in a
Microprocessor?
-
What is ACBF(Hex) divided by 16?
-
Convert 65(Hex) to Binary
-
Convert a number to its two’s
compliment and back
-
The CPU is busy but you want to stop
and do some other task. How do you
do it? </>
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